1. Field of the Invention
The present invention relates to a microprocessor incorporating a synchronous type memory on the same chip.
2. Description of the Related Art
FIG. 1 is a timing chart showing a state of operation of a two-port RAM which was reported as "Two-port data RAM of DSSP1" in National Convention Record, 1985, The Institute of Electronics and Communication Engineers of Japan as an example of a conventional microprocessor.
A synchronous type memory constituted with a two-port RAM pre-charges bit line, drives word line, operates sense amplifier- and the like on a machine cycle basis, for example, using four-phase clocks of a general purpose speech signal processor (DSSP1: Digital Speech Signal Processor). Hereinafter specific description is made thereon.
Here, one machine cycle is divided into four durations T1, T2, T3 and T4 responding to each duration of high level "H" of four-phase clocks.
In the duration T1, pre-charge of bit lines and decode of an address signal is performed as shown in FIG. 1(a) and FIG. 1(b), respectively.
In the duration T2, the bit lines are discharged to read data into the bit, lines as shown in FIG. 1(d), and during the duration T2 through the duration T4, word lines are driven as shown in FIG. 1(c).
Also, during the durations T3 and T4, operation of a sense amplifier and operation of an output buffer are performed as shown in FIG. 1(e) and FIG. 1(f), respectively.
Needless to say, power is consumed attending on a level change of each signal line during the above-described one machine cycle.
FIG. 2 is a block diagram showing a configuration of a synchronous type memory performing the operations as described above.
In FIG. 2, numeral 9 designates a one-chip microprocessor, which is constituted by incorporating a CPU 10, a synchronous type memory 3 and the like.
The CPU 10 is constituted within an instruction register 1, an instruction decoder 2, an ALU (Arithmetic and Logic Unit) which is not illustrated and the like.
The instruction register 1 holds an instruction to be executed. Also, the instruction decoder 2 decodes the instruction held in the instruction register 1.
The synchronous type memory 3 is constituted with an address decoder 31, a sense amplifier 32, a pre-charging circuit 33, a memory cell array 34 and the like, and stores various data in the memory cell array 34.
Numeral 4 designates address signal lines, which input an address signal representing the memory location of data to be accessed by the CPU 10 in the synchronous type memory 3 to the address decoder 31.
The address decoder 31 decodes the address signal inputted through the address signal lines 4, and outputs the decoded result to the memory cell array 34 through word lines 35.
Numeral 5 designates output data signal lines. A signal of data read from the memory cell array 34 is amplified by the sense amplifier 32, being outputted to the output data signal lines 5.
Numeral 6 designates four-phase clock lines, which transmit a four-phase clock to the above-described address decoder 31 and the pre-charging circuit 33 and the sense amplifier 32 as described later.
The pre-charging circuit 33 pre-charges bit lines 36 of the memory cell array 34.
In such a one-chip microprocessor 9, the synchronous type memory 3 performs reading operation all the time in synchronism with the clock given through the four-phase clock lines 6 even in the duration when it is not accessed by the CPU 10.
In the conventional microprocessor incorporating the synchronous type memory as described above, even when the CPU does not necessitate an access to the synchronous type memory, the synchronous type memory performs reading operation by a clock supplied on a cycle basis. This means that it performs sequential operations for reading data of bit line pre-charge, address decode and word line drive on a cycle bases. For this reason, there exists a problem of consuming unnecessary power.
In the light of such circumstances, for example, the invention of the Japanese Patent Application Laid-Open No. 63-26716(1988) purposing a reduction in power consumption of the microprocessor has been proposed.
This invention of the Japanese Patent Application Laid-Open No. 63-26716(1988) detects a function block in the microprocessor which does not operate in decoding an instruction, and does not make the block operate by stopping supply of the clock, and thereby power consumption is curtailed.
However, this invention of the Japanese Patent Application Laid-Open No. 63-26716(1988) is constituted in a manner that clock supply to each function block in the microprocessor is distributed by a clock distributing circuit, and the clock supply to each function block is stopped by this clock distributing circuit. Accordingly, in the above-described invention of the Japanese Patent Application Laid-Open No. 63-26716(1988), the clock supply to each function block is stopped on a function block basis.
Then, in the above-described Japanese Patent Application Laid-Open No. 63-26716(1988), a built-in synchronous type memory is not shown as a function block in the microprocessor, but in the microprocessor incorporating a large capacity memory on the chip, the greater part of the power thereof is consumed by the memory. Then, it is considered that this invention of the Japanese Patent Application Laid-Open No. 63-26716(1988) is applied to the microprocessor incorporating the synchronous type memory as a function block, but in this case, clock supply to the whole of the memory is stopped. However, as shown in FIG. 2, the memory is normally divided into the portions of the address decoder, the word line driving circuit, the bit line pre-charging circuit, the sense amplifier and the like. For this reason, where clock supply is stopped uniformly for the whole memory as described above, supply and stop of clock in response to the status of each portion of the memory cannot be carried out, and therefore various troubles might take place.
For example, in a circuit construction in which addresses are decoded during durations of "H" of the clock and the word lines are driven during durations of "L" of the clock, the word lines are desirably made non-active, in other words, the clock supply is desirably stopped at its state of "H" in order to protect the stored contents of the memory. However, when the clock supply is stopped to do so, the decoder is put intact in the operated state, and there is possibility of power consumption.